1. Field of the Invention
The present invention belongs to the field of design technology for large-scale semiconductor integrated circuits containing so-called processors (SoC: System on Chip), and particularly relates to a skeleton generation apparatus and method for generating a skeleton of a system model in ESL (Electronic System Level) design for developing an electronic system adapted to realize the processing of simultaneous and concurrent behaviors of function blocks that is required in large-scale integrated circuits, by means of a system level design language from a programming language for general sequential processing used for algorithm development.
2. Description of Related Art
In general, design techniques using system level design languages make it necessary to clearly define inputs and outputs of function blocks, and in this regard differ from programming languages generally used for algorithm development, which permit various direct or indirect inputs and outputs such as global variables and pointer accesses.
To make up this difference, steady effort has been made to accomplish function blocking that performs rewriting to define inputs and outputs with arguments and return values at algorithm levels, i.e., programming language levels.
However, it is extremely difficult for a user to understand the content of processing and arrange variables on the basis of the source of a programming language which is made of various units developed and described by different programmers other than the user. Modifications at programming language levels do not offer means for detecting unexpected uses of variables, and problems are tend to be buried and not become evident, so that initial start-up takes long time.
In view of such situation, it has been proposed to provide various apparatuses and methods for converting information on hardware specifications into hardware design description languages (refer to Patent Literatures 1 to 5 by way of example).
Patent Literature 1 (Japanese Patent Application Publication Number 07-306879) discloses a netlist and hardware description conversion apparatus for generating a hardware description language source from a netlist and realizing conversion to function level design using the hardware description language.
Patent Literature 2 (Japanese Patent Application Publication Number 07-086886) discloses the technique of converting logic information representative of logic or functions in the form of lists or formulae into a hardware connection description language from the lists or the formulas.
Patent Literature 3 (Japanese Patent Application Publication Number 04-042372) discloses a logic circuit editing system which includes representation form conversion means for converting an existing logic circuit into a representation form of function level, input edit means for performing input edit of a new logic circuit by using the existing logic circuit represented in the form of function level, and database registration means for registering an objective logic circuit obtained by input edit in a database.
Patent Literature 4 (Japanese Patent Publication Number 3033091) discloses the technique of interpreting individual logic functions into a logic simulation description language while interpreting an edit command table.
Patent Literature 5 (Japanese Patent Application Publication Number 2004-220223) discloses an information processing apparatus which, on the basis of input hardware external specifications information, generates a port definition file described in a system description language, generates a port-to-port connection definition file described in the system description language, generates a port-related function definition file described in the system description language, and generates a hardware model input/output function definition file described in the system description language.